[notify] llvm: AVX Incorrect code created, regression from 11.0
This commit is contained in:
Danny Rawlins
parent
3aa194e76f
commit
48be304345
@ -1785,6 +1785,10 @@ drwxr-xr-x root/root usr/include/llvm/XRay/
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-rw-r--r-- root/root usr/include/llvm/XRay/XRayRecord.h
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-rw-r--r-- root/root usr/include/llvm/XRay/YAMLXRayRecord.h
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drwxr-xr-x root/root usr/lib/
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-rwxr-xr-x root/root usr/lib/LLVMgold.so
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drwxr-xr-x root/root usr/lib/bfd-plugins/
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lrwxrwxrwx root/root usr/lib/bfd-plugins/LLVMgold.so -> ../LLVMgold.so
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lrwxrwxrwx root/root usr/lib/bfd-plugins/libLTO.so -> ../libLTO.so
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drwxr-xr-x root/root usr/lib/cmake/
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drwxr-xr-x root/root usr/lib/cmake/llvm/
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-rw-r--r-- root/root usr/lib/cmake/llvm/AddLLVM.cmake
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@ -1,6 +1,7 @@
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untrusted comment: verify with /etc/ports/opt.pub
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RWSE3ohX2g5d/b8fnC7+uNHjU1yDzP/CIRZLz+sG61eQ8zTdOTyABXYePuft4IV0vQE3eACQ8ZS+8wU9tFGmzzVLCqsQ7JSaCgU=
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SHA256 (Pkgfile) = 3d766fd1342ee2d65a6fe50e1c74406b2362f8b97575fa44412954179ce72a5b
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SHA256 (.footprint) = 567f94d08ad018de2dbafdaa6ac34f4999d94a2cf375545d1be04df1145ac2e9
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RWSE3ohX2g5d/RvBcyu+jCK65JXJDZ6er+abNe55RrStJabtoYld2V4iDq+k+P6S0cNDiKcjuRugGvXT2bFZmID+mQHyFSvnmws=
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SHA256 (Pkgfile) = 2b6af98c5f86a0eb035e7de004cc7c9f8efa0fa5c7fd4408206ebdc396082453
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SHA256 (.footprint) = 39108efa76f0fb409c02917e07c43dc31cbd1e4363f260c4a96bc6cce67da0a2
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SHA256 (llvm-12.0.1.src.tar.xz) = 7d9a8405f557cefc5a21bf5672af73903b64749d9bc3a50322239f56f34ffddf
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SHA256 (llvm-config.h) = 2227b83b904348e5530f3475c978e11cb0f05a85024781dcb49ac86b65582707
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SHA256 (x86-twist-shuffle-mask.patch) = c51b8754f76eb3774f46d530409f6d89f5bb47d90f0d718dbfa861f716b29693
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14
llvm/Pkgfile
14
llvm/Pkgfile
@ -5,11 +5,16 @@
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name=llvm
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version=12.0.1
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release=1
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release=2
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source=(https://github.com/llvm/llvm-project/releases/download/llvmorg-$version/llvm-$version.src.tar.xz
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llvm-config.h)
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llvm-config.h
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x86-twist-shuffle-mask.patch)
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build() {
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# https://reviews.llvm.org/D104903
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# https://bugs.llvm.org/show_bug.cgi?id=50823
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patch -d $name-$version.src -p2 -i $SRC/x86-twist-shuffle-mask.patch
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export CC=gcc
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export CXX=g++
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@ -19,6 +24,7 @@ build() {
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-D CMAKE_C_FLAGS_RELEASE="$CFLAGS" \
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-D CMAKE_CXX_FLAGS_RELEASE="$CXXFLAGS" \
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-D LLVM_TARGETS_TO_BUILD='X86;AMDGPU;BPF;NVPTX' \
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-D LLVM_BINUTILS_INCDIR=/usr/include \
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-D LLVM_BUILD_LLVM_DYLIB=1 \
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-D LLVM_LINK_LLVM_DYLIB=1 \
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-D LLVM_PARALLEL_COMPILE_JOBS="${JOBS:-1}" \
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@ -36,4 +42,8 @@ build() {
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# multilib stub
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mv $PKG/usr/include/llvm/Config/llvm-config{,-64}.h
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install -m 0644 $SRC/llvm-config.h $PKG/usr/include/llvm/Config/
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install -d $PKG/usr/lib/bfd-plugins
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ln -s ../LLVMgold.so $PKG/usr/lib/bfd-plugins/
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ln -s ../libLTO.so $PKG/usr/lib/bfd-plugins/
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}
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117
llvm/x86-twist-shuffle-mask.patch
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117
llvm/x86-twist-shuffle-mask.patch
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@ -0,0 +1,117 @@
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From 2c3bca2c3f13a0a9ef71d549a90fba23e6997d44 Mon Sep 17 00:00:00 2001
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From: "Wang, Pengfei" <pengfei.wang@intel.com>
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Date: Mon, 5 Jul 2021 21:08:49 +0800
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Subject: [PATCH] Twist shuffle mask when fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y))
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-> SHUFFLE(HOP(X,Y))
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This patch fixes PR50823.
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The shuffle mask should be twisted twice before gotten the correct one due to the difference between inner HOP and outer.
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Reviewed By: RKSimon
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Differential Revision: https://reviews.llvm.org/D104903
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(cherry picked from commit 9ab99f773fec7da4183495a3fdc655a797d3bea2)
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---
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llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++---
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llvm/test/CodeGen/X86/haddsub-undef.ll | 4 +--
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llvm/test/CodeGen/X86/packss.ll | 2 +-
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llvm/test/CodeGen/X86/pr50823.ll | 35 +++++++++++++++++++++++++
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4 files changed, 42 insertions(+), 6 deletions(-)
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create mode 100644 llvm/test/CodeGen/X86/pr50823.ll
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
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index 1e2407c7e7f6..d8b2f765e953 100644
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--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
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+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
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@@ -43194,9 +43194,10 @@ static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG,
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ShuffleVectorSDNode::commuteMask(ShuffleMask1);
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}
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if ((Op00 == Op10) && (Op01 == Op11)) {
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- SmallVector<int, 4> ShuffleMask;
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- ShuffleMask.append(ShuffleMask0.begin(), ShuffleMask0.end());
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- ShuffleMask.append(ShuffleMask1.begin(), ShuffleMask1.end());
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+ const int Map[4] = {0, 2, 1, 3};
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+ SmallVector<int, 4> ShuffleMask(
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+ {Map[ShuffleMask0[0]], Map[ShuffleMask1[0]], Map[ShuffleMask0[1]],
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+ Map[ShuffleMask1[1]]});
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SDLoc DL(N);
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MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
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SDValue Res = DAG.getNode(Opcode, DL, VT, Op00, Op01);
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diff --git a/llvm/test/CodeGen/X86/haddsub-undef.ll b/llvm/test/CodeGen/X86/haddsub-undef.ll
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index 68d058433179..e7c8b84d3bc7 100644
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--- a/llvm/test/CodeGen/X86/haddsub-undef.ll
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+++ b/llvm/test/CodeGen/X86/haddsub-undef.ll
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@@ -1166,7 +1166,7 @@ define <4 x double> @PR34724_add_v4f64_u123(<4 x double> %0, <4 x double> %1) {
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; AVX512-FAST: # %bb.0:
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; AVX512-FAST-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX512-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
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-; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,0,3]
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+; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3]
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; AVX512-FAST-NEXT: retq
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%3 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 2, i32 4>
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%4 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 3, i32 5>
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@@ -1267,7 +1267,7 @@ define <4 x double> @PR34724_add_v4f64_01u3(<4 x double> %0, <4 x double> %1) {
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; AVX512-FAST-LABEL: PR34724_add_v4f64_01u3:
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; AVX512-FAST: # %bb.0:
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; AVX512-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
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-; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,1,3]
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+; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3]
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; AVX512-FAST-NEXT: retq
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%3 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 0, i32 2>
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%4 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 1, i32 3>
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diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
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index 16349ae2c7f9..ac431b7556ea 100644
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--- a/llvm/test/CodeGen/X86/packss.ll
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+++ b/llvm/test/CodeGen/X86/packss.ll
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@@ -370,7 +370,7 @@ define <32 x i8> @packsswb_icmp_zero_trunc_256(<16 x i16> %a0) {
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpacksswb %ymm0, %ymm1, %ymm0
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-; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3]
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+; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,3]
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; AVX2-NEXT: ret{{[l|q]}}
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%1 = icmp eq <16 x i16> %a0, zeroinitializer
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%2 = sext <16 x i1> %1 to <16 x i16>
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diff --git a/llvm/test/CodeGen/X86/pr50823.ll b/llvm/test/CodeGen/X86/pr50823.ll
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new file mode 100644
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index 000000000000..c5d5296e5c66
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--- /dev/null
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+++ b/llvm/test/CodeGen/X86/pr50823.ll
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@@ -0,0 +1,35 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
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+
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+%v8_uniform_FVector3 = type { float, float, float }
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+
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+declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
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+
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+define void @foo(%v8_uniform_FVector3* %Out, float* %In, <8 x i32> %__mask) {
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+; CHECK-LABEL: foo:
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+; CHECK: # %bb.0: # %allocas
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+; CHECK-NEXT: vmovups (%rsi), %xmm0
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+; CHECK-NEXT: vhaddps 32(%rsi), %xmm0, %xmm0
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+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,1]
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+; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0
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+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
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+; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0
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+; CHECK-NEXT: vmovss %xmm0, (%rdi)
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+; CHECK-NEXT: vzeroupper
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+; CHECK-NEXT: retq
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+allocas:
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+ %ptr_cast_for_load = bitcast float* %In to <8 x float>*
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+ %ptr_masked_load74 = load <8 x float>, <8 x float>* %ptr_cast_for_load, align 4
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+ %ptr8096 = getelementptr float, float* %In, i64 8
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+ %ptr_cast_for_load81 = bitcast float* %ptr8096 to <8 x float>*
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+ %ptr80_masked_load82 = load <8 x float>, <8 x float>* %ptr_cast_for_load81, align 4
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+ %ret_7.i.i = shufflevector <8 x float> %ptr_masked_load74, <8 x float> %ptr80_masked_load82, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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+ %Out_load19 = getelementptr %v8_uniform_FVector3, %v8_uniform_FVector3* %Out, i64 0, i32 0
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+ %v1.i.i100 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %ret_7.i.i, <8 x float> %ret_7.i.i)
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+ %v2.i.i101 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %v1.i.i100, <8 x float> %v1.i.i100)
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+ %scalar1.i.i102 = extractelement <8 x float> %v2.i.i101, i32 0
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+ %scalar2.i.i103 = extractelement <8 x float> %v2.i.i101, i32 4
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+ %sum.i.i104 = fadd float %scalar1.i.i102, %scalar2.i.i103
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+ store float %sum.i.i104, float* %Out_load19, align 4
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+ ret void
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+}
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