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Fix misdetected Slow_SSE4_2 cpu feature bit (bug 17501)

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Andreas Schwab 2014-10-21 11:09:19 +02:00
parent 461a7b1e45
commit 3574f2fdf3
6 changed files with 21 additions and 11 deletions
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10
ChangeLog
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@ -1,3 +1,13 @@
2014-10-27 Andreas Schwab <schwab@suse.de>
[BZ #17501]
* sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Fix
check for Slow_SSE4_2 feature bit.
* sysdeps/i386/i686/multiarch/strcmp.S (STRCMP): Likewise.
* sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
* sysdeps/x86_64/multiarch/strcmp.S (STRCMP, __strcascmp):
Likewise. Fix check for Fast_Unaligned_Load feature bit.
2014-10-24 Roland McGrath <roland@hack.frob.com> 2014-10-24 Roland McGrath <roland@hack.frob.com>
* configure.ac: Validate compiler version with a empirical test of * configure.ac: Validate compiler version with a empirical test of

2
NEWS
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@ -10,7 +10,7 @@ Version 2.21
* The following bugs are resolved with this release: * The following bugs are resolved with this release:
6652, 12926, 14171, 15884, 17266, 17363, 17370, 17371, 17411, 17460, 6652, 12926, 14171, 15884, 17266, 17363, 17370, 17371, 17411, 17460,
17485, 17508. 17485, 17501, 17508.
Version 2.20 Version 2.20

4
sysdeps/i386/i686/multiarch/strcasecmp.S
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@ -37,7 +37,7 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f jnz 2f
leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx 2: popl %ebx
@ -58,7 +58,7 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3, %eax leal __strcasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f jnz 2f
leal __strcasecmp_sse4_2, %eax leal __strcasecmp_sse4_2, %eax
2: ret 2: ret

4
sysdeps/i386/i686/multiarch/strcmp.S
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@ -68,7 +68,7 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f jnz 2f
leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax
2: popl %ebx 2: popl %ebx
@ -89,7 +89,7 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3, %eax leal __STRCMP_SSSE3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f jnz 2f
leal __STRCMP_SSE4_2, %eax leal __STRCMP_SSE4_2, %eax
2: ret 2: ret

4
sysdeps/i386/i686/multiarch/strncase.S
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@ -37,7 +37,7 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f jnz 2f
leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx 2: popl %ebx
@ -58,7 +58,7 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3, %eax leal __strncasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f jnz 2f
leal __strncasecmp_sse4_2, %eax leal __strncasecmp_sse4_2, %eax
2: ret 2: ret

8
sysdeps/x86_64/multiarch/strcmp.S
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@ -91,10 +91,10 @@ ENTRY(STRCMP)
1: 1:
#ifdef USE_AS_STRCMP #ifdef USE_AS_STRCMP
leaq __strcmp_sse2_unaligned(%rip), %rax leaq __strcmp_sse2_unaligned(%rip), %rax
testl $bit_Fast_Unaligned_Load, __cpu_features+CPUID_OFFSET+index_Fast_Unaligned_Load(%rip) testl $bit_Fast_Unaligned_Load, __cpu_features+FEATURE_OFFSET+index_Fast_Unaligned_Load(%rip)
jnz 3f jnz 3f
#else #else
testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f jnz 2f
leaq STRCMP_SSE42(%rip), %rax leaq STRCMP_SSE42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@ -120,7 +120,7 @@ ENTRY(__strcasecmp)
testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip) testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
jnz 3f jnz 3f
# endif # endif
testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f jnz 2f
leaq __strcasecmp_sse42(%rip), %rax leaq __strcasecmp_sse42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@ -146,7 +146,7 @@ ENTRY(__strncasecmp)
testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip) testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
jnz 3f jnz 3f
# endif # endif
testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip) testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f jnz 2f
leaq __strncasecmp_sse42(%rip), %rax leaq __strncasecmp_sse42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)