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(_FPU_GETCW): Allow gcc to generic postinc/postdec instruction. (_FPU_SETCW): Likewise.

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Ulrich Drepper 2000-08-20 16:42:35 +00:00
parent 768b07329e
commit 479a9deb9a
1 changed files with 2 additions and 2 deletions
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4
sysdeps/powerpc/fpu_control.h
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@ -51,14 +51,14 @@ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
/* Macros for accessing the hardware control word. */ /* Macros for accessing the hardware control word. */
#define _FPU_GETCW(cw) ( { \ #define _FPU_GETCW(cw) ( { \
union { double d; fpu_control_t cw[2]; } tmp __attribute__ ((__aligned__(8))); \ union { double d; fpu_control_t cw[2]; } tmp __attribute__ ((__aligned__(8))); \
__asm__ ("mffs 0; stfd 0,%0" : "=m" (tmp.d) : : "fr0"); \ __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
(cw)=tmp.cw[1]; \ (cw)=tmp.cw[1]; \
tmp.cw[1]; } ) tmp.cw[1]; } )
#define _FPU_SETCW(cw) { \ #define _FPU_SETCW(cw) { \
union { double d; fpu_control_t cw[2]; } tmp __attribute__ ((__aligned__(8))); \ union { double d; fpu_control_t cw[2]; } tmp __attribute__ ((__aligned__(8))); \
tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \ tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
tmp.cw[1] = cw; \ tmp.cw[1] = cw; \
__asm__ ("lfd 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \ __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
} }
/* Default control word set at startup. */ /* Default control word set at startup. */