2015-01-05 Steve Ellcey <sellcey@imgtec.com>
* sysdeps/mips/memcpy.S: Add support for mips32r6/mips64r6.
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Steve Ellcey
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@ -1,3 +1,7 @@
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2015-01-05 Steve Ellcey <sellcey@imgtec.com>
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* sysdeps/mips/memcpy.S: Add support for mips32r6/mips64r6.
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2015-01-05 Joseph Myers <joseph@codesourcery.com>
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[BZ #17796]
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@ -51,6 +51,13 @@
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#endif
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#if __mips_isa_rev > 5
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# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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# undef PREFETCH_STORE_HINT
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# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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# endif
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# define R6_CODE
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#endif
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/* Some asm.h files do not have the L macro definition. */
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#ifndef L
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@ -79,6 +86,14 @@
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# endif
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#endif
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/* New R6 instructions that may not be in asm.h. */
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#ifndef PTR_LSA
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# if _MIPS_SIM == _ABI64
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# define PTR_LSA dlsa
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# else
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# define PTR_LSA lsa
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# endif
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#endif
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/*
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* Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load
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@ -221,6 +236,7 @@
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# define C_LDLO ldl /* low part is left in little-endian */
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# define C_STLO sdl /* low part is left in little-endian */
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# endif
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# define C_ALIGN dalign /* r6 align instruction */
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#else
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# define C_ST sw
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# define C_LD lw
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@ -235,6 +251,7 @@
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# define C_LDLO lwl /* low part is left in little-endian */
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# define C_STLO swl /* low part is left in little-endian */
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# endif
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# define C_ALIGN align /* r6 align instruction */
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#endif
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/* Bookkeeping values for 32 vs. 64 bit mode. */
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@ -285,6 +302,9 @@ L(memcpy):
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#else
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move v0,a0
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#endif
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#ifndef R6_CODE
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/*
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* If src and dst have different alignments, go to L(unaligned), if they
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* have the same alignment (but are not actually aligned) do a partial
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@ -305,6 +325,74 @@ L(memcpy):
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C_STHI t8,0(a0)
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PTR_ADDU a0,a0,a3
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#else /* R6_CODE */
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/*
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* Align the destination and hope that the source gets aligned too. If it
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* doesn't we jump to L(r6_unaligned*) to do unaligned copies using the r6
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* align instruction.
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*/
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andi t8,a0,7
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lapc t9,L(atable)
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PTR_LSA t9,t8,t9,2
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jrc t9
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L(atable):
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bc L(lb0)
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bc L(lb7)
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bc L(lb6)
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bc L(lb5)
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bc L(lb4)
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bc L(lb3)
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bc L(lb2)
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bc L(lb1)
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L(lb7):
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lb a3, 6(a1)
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sb a3, 6(a0)
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L(lb6):
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lb a3, 5(a1)
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sb a3, 5(a0)
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L(lb5):
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lb a3, 4(a1)
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sb a3, 4(a0)
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L(lb4):
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lb a3, 3(a1)
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sb a3, 3(a0)
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L(lb3):
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lb a3, 2(a1)
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sb a3, 2(a0)
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L(lb2):
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lb a3, 1(a1)
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sb a3, 1(a0)
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L(lb1):
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lb a3, 0(a1)
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sb a3, 0(a0)
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li t9,8
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subu t8,t9,t8
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PTR_SUBU a2,a2,t8
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PTR_ADDU a0,a0,t8
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PTR_ADDU a1,a1,t8
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L(lb0):
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andi t8,a1,(NSIZE-1)
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lapc t9,L(jtable)
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PTR_LSA t9,t8,t9,2
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jrc t9
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L(jtable):
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bc L(aligned)
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bc L(r6_unaligned1)
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bc L(r6_unaligned2)
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bc L(r6_unaligned3)
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# ifdef USE_DOUBLE
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bc L(r6_unaligned4)
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bc L(r6_unaligned5)
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bc L(r6_unaligned6)
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bc L(r6_unaligned7)
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# endif
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#endif /* R6_CODE */
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L(aligned):
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/*
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* Now dst/src are both aligned to (word or double word) aligned addresses
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* Set a2 to count how many bytes we have to copy after all the 64/128 byte
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@ -313,7 +401,6 @@ L(memcpy):
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* equals a3.
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*/
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L(aligned):
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andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
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beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */
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PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
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@ -363,8 +450,12 @@ L(loop16w):
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bgtz v1,L(skip_pref)
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#endif
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C_LD t1,UNIT(1)(a1)
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#ifdef R6_CODE
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PREFETCH_FOR_STORE (2, a0)
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#else
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PREFETCH_FOR_STORE (4, a0)
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PREFETCH_FOR_STORE (5, a0)
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#endif
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#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH)
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5)
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# ifdef USE_DOUBLE
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@ -378,8 +469,11 @@ L(skip_pref):
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C_LD REG5,UNIT(5)(a1)
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C_LD REG6,UNIT(6)(a1)
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C_LD REG7,UNIT(7)(a1)
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PREFETCH_FOR_LOAD (4, a1)
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#ifdef R6_CODE
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PREFETCH_FOR_LOAD (3, a1)
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#else
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PREFETCH_FOR_LOAD (4, a1)
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#endif
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C_ST t0,UNIT(0)(a0)
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C_ST t1,UNIT(1)(a0)
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C_ST REG2,UNIT(2)(a0)
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@ -397,7 +491,9 @@ L(skip_pref):
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C_LD REG5,UNIT(13)(a1)
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C_LD REG6,UNIT(14)(a1)
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C_LD REG7,UNIT(15)(a1)
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#ifndef R6_CODE
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PREFETCH_FOR_LOAD (5, a1)
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#endif
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C_ST t0,UNIT(8)(a0)
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C_ST t1,UNIT(9)(a0)
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C_ST REG2,UNIT(10)(a0)
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@ -476,6 +572,8 @@ L(lastbloop):
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L(leave):
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j ra
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nop
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#ifndef R6_CODE
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/*
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* UNALIGNED case, got here with a3 = "negu a0"
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* This code is nearly identical to the aligned code above
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@ -510,38 +608,38 @@ L(ua_chk16w):
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PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
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PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
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PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
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#endif
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# endif
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PREFETCH_FOR_LOAD (0, a1)
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PREFETCH_FOR_LOAD (1, a1)
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PREFETCH_FOR_LOAD (2, a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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PREFETCH_FOR_STORE (1, a0)
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PREFETCH_FOR_STORE (2, a0)
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PREFETCH_FOR_STORE (3, a0)
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#endif
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#if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
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# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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# endif
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# if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
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# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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bgtz v1,L(ua_skip_set)
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nop
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
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L(ua_skip_set):
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# else
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# else
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
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# endif
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# endif
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#endif
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L(ua_loop16w):
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PREFETCH_FOR_LOAD (3, a1)
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C_LDHI t0,UNIT(0)(a1)
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C_LDHI t1,UNIT(1)(a1)
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C_LDHI REG2,UNIT(2)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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bgtz v1,L(ua_skip_pref)
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#endif
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# endif
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C_LDHI REG3,UNIT(3)(a1)
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PREFETCH_FOR_STORE (4, a0)
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PREFETCH_FOR_STORE (5, a0)
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@ -667,6 +765,59 @@ L(ua_smallCopy_loop):
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j ra
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nop
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#else /* R6_CODE */
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# if __MIPSEB
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# define SWAP_REGS(X,Y) X, Y
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# define ALIGN_OFFSET(N) (N)
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# else
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# define SWAP_REGS(X,Y) Y, X
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# define ALIGN_OFFSET(N) (NSIZE-N)
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# endif
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# define R6_UNALIGNED_WORD_COPY(BYTEOFFSET) \
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andi REG7, a2, (NSIZE-1);/* REG7 is # of bytes to by bytes. */ \
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beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \
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PTR_SUBU a3, a2, REG7; /* a3 is number of bytes to be copied in */ \
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/* (d)word chunks. */ \
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move a2, REG7; /* a2 is # of bytes to copy byte by byte */ \
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/* after word loop is finished. */ \
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PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \
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PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \
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PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \
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C_LD t0, UNIT(0)(REG2); /* Load first part of source. */ \
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L(r6_ua_wordcopy##BYTEOFFSET): \
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C_LD t1, UNIT(1)(REG2); /* Load second part of source. */ \
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C_ALIGN REG3, SWAP_REGS(t1,t0), ALIGN_OFFSET(BYTEOFFSET); \
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PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \
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PTR_ADDIU REG2, REG2, UNIT(1); /* Increment aligned source pointer.*/ \
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move t0, t1; /* Move second part of source to first. */ \
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bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \
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C_ST REG3, UNIT(-1)(a0); \
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j L(lastb); \
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nop
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/* We are generating R6 code, the destination is 4 byte aligned and
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the source is not 4 byte aligned. t8 is 1, 2, or 3 depending on the
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alignment of the source. */
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L(r6_unaligned1):
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R6_UNALIGNED_WORD_COPY(1)
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L(r6_unaligned2):
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R6_UNALIGNED_WORD_COPY(2)
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L(r6_unaligned3):
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R6_UNALIGNED_WORD_COPY(3)
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# ifdef USE_DOUBLE
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L(r6_unaligned4):
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R6_UNALIGNED_WORD_COPY(4)
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L(r6_unaligned5):
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R6_UNALIGNED_WORD_COPY(5)
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L(r6_unaligned6):
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R6_UNALIGNED_WORD_COPY(6)
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L(r6_unaligned7):
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R6_UNALIGNED_WORD_COPY(7)
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# endif
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#endif /* R6_CODE */
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.set at
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.set reorder
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END(MEMCPY_NAME)
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