powerpc: setcontext.S uses power6 mtfsf when not supported [BZ #18116]
The attached patch fixes a glibc build failure with gcc 5 on powerpc64le caused by a recent change in gcc where the compiler defines the _ARCH_PWR6 macro when processing assembly files but doesn't invoke the assembler in the corresponding machine mode (unless it has been explicitly configured to target POWER 6 or later). A bug had been filed with gcc for this (65341) but was closed as won't fix. Glibc relies on the _ARCH_PWR6 macro in a few .S files to make use of Power ISA 2.5 instructions (specifically, the four-argument form of the mtfsf insn). A similar problem had occurred in the past (bug 10118) but the fix that was committed for it didn't anticipate this new problem.
This commit is contained in:
Martin Sebor
Tulio Magno Quites Machado Filho
parent
0cd2828695
commit
db8fed87d9
@ -1,3 +1,12 @@
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2015-03-11 Martin Sebor <msebor@redhat.com>
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[BZ #18116]
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* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
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(__setcontext): Use extended four-operand version of mtsf whenever
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possible.
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* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
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(__novec_swapcontext): Likewise.
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2015-06-01 Siddhesh Poyarekar <siddhesh@redhat.com>
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* benchtests/scripts/compare_bench.py: New file.
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@ -81,22 +81,31 @@ ENTRY(__novec_setcontext)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r5,PPC_FEATURE_HAS_DFP
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beq 5f
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/* Use the extended four-operand version of the mtfsf insn. */
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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b 6f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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5:
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mtfsf 0xff,fp0
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6:
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.machine pop
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# endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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@ -364,22 +373,31 @@ L(has_no_vec):
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r5,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7:
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mtfsf 0xff,fp0
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8:
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.machine pop
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# endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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@ -173,24 +173,34 @@ ENTRY(__novec_swapcontext)
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lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
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lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
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lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r8,PPC_FEATURE_HAS_DFP
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beq 5f
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/* Use the extended four-operand version of the mtfsf insn. */
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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b 6f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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5:
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mtfsf 0xff,fp0
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6:
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.machine pop
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#endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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@ -652,24 +662,34 @@ L(has_no_vec2):
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lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
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lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
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lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
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# ifdef _ARCH_PWR6
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/* Use the extended four-operand version of the mtfsf insn. */
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mtfsf 0xff,fp0,1,0
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# else
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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# else
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/* Availability of DFP indicates a 64-bit FPSCR. */
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andi. r6,r8,PPC_FEATURE_HAS_DFP
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beq 7f
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/* Use the extended four-operand version of the mtfsf insn. */
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.machine push
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.machine "power6"
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mtfsf 0xff,fp0,1,0
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.machine pop
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b 8f
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/* Continue to operate on the FPSCR as if it were 32-bits. */
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7:
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mtfsf 0xff,fp0
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8:
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.machine pop
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#endif /* _ARCH_PWR6 */
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lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
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lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
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lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
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