system/glibc
3
0
Fork 0
Code Issues Projects Releases Wiki Activity

[BZ #2505]

Browse Source 
2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>
	[BZ #2505]
	* sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
	Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.
This commit is contained in:
Roland McGrath 2006-04-04 08:18:56 +00:00
parent 729f7b28c5
commit f9d35bb91e
3 changed files with 36 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChangeLog
View File

@ -10,6 +10,12 @@
($(objpfx)iso8859-7jp.stmp): Likewise.
Reported by S.Çağlar Onur <caglar@uludag.org.tr>.
2006-04-03 Steven Munroe <sjmunroe@us.ibm.com>
[BZ #2505]
* sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.
2006-04-03 Andreas Schwab <schwab@suse.de>
* sysdeps/unix/sysv/linux/powerpc/powerpc32/clone.S: Terminate FDE

16
nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
View File

@ -110,7 +110,21 @@
# define __lll_rel_instr ""
#else
# define __lll_acq_instr "isync"
# define __lll_rel_instr "sync"
# ifdef _ARCH_PWR4
/*
* Newer powerpc64 processors support the new "light weight" sync (lwsync)
* So if the build is using -mcpu=[power4,power5,power5+,970] we can
* safely use lwsync.
*/
# define __lll_rel_instr "lwsync"
# else
/*
* Older powerpc32 processors don't support the new "light weight"
* sync (lwsync). So the only safe option is to use normal sync
* for all powerpc32 applications.
*/
# define __lll_rel_instr "sync"
# endif
#endif
/* Set *futex to ID if it is 0, atomically. Returns the old value */

15
sysdeps/powerpc/powerpc32/bits/atomic.h
View File

@ -89,12 +89,27 @@
# define __arch_atomic_decrement_if_positive_64(mem) \
({ abort (); (*mem)--; })
#ifdef _ARCH_PWR4
/*
* Newer powerpc64 processors support the new "light weight" sync (lwsync)
* So if the build is using -mcpu=[power4,power5,power5+,970] we can
* safely use lwsync.
*/
# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
/*
* "light weight" sync can also be used for the release barrier.
*/
# ifndef UP
# define __ARCH_REL_INSTR "lwsync"
# endif
#else
/*
* Older powerpc32 processors don't support the new "light weight"
* sync (lwsync). So the only safe option is to use normal sync
* for all powerpc32 applications.
*/
# define atomic_read_barrier() __asm ("sync" ::: "memory")
#endif
/*
* Include the rest of the atomic ops macros which are common to both