1b6e07f8e0
Support added to identify Sparc M7/T7/S7/M8/T8 processor capability. Performance tests run on Sparc S7 using new code and old niagara4 code. Optimizations for memcpy also apply to mempcpy and memmove where they share code. Optimizations for memset also apply to bzero as they share code. For memcpy/mempcpy/memmove, performance comparison with niagara4 code: Long word aligned data 0-127 bytes - minimal changes 128-1023 bytes - 7-30% gain 1024+ bytes - 1-7% gain (in cache); 30-100% gain (out of cache) Word aligned data 0-127 bytes - 50%+ gain 128-1023 bytes - 10-200% gain 1024+ bytes - 0-15% gain (in cache); 5-50% gain (out of cache) Unaligned data 0-127 bytes - 0-70%+ gain 128-447 bytes - 40-80%+ gain 448-511 bytes - 1-3% loss 512-4096 bytes - 2-3% gain (in cache); 0-20% gain (out of cache) 4096+ bytes - ± 3% (in cache); 20-50% gain (out of cache) Tested in sparcv9-*-* and sparc64-*-* targets in both multi and non-multi arch configurations. Patrick McGehearty <patrick.mcgehearty@oracle.com> Adhemerval Zanella <adhemerval.zanella@linaro.org> * sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile (sysdeps_routines): Add memcpy-memmove-niagara7 and memmove-ultra1. * sysdeps/sparc/sparc64/multiarch/Makefile (sysdeps_routines): Likewise. * sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-memmove-niagara7.S: New file. * sysdeps/sparc/sparc32/sparcv9/multiarch/memmove-ultra1.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memmove.c: Likewise. * sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list): Add __memcpy_niagara7, __mempcpy_niagara7, and __memmove_niagara7. * sysdeps/sparc/sparc64/multiarch/ifunc-memcpy.h (IFUNC_SELECTOR): Add niagara7 option. * sysdeps/sparc/sparc64/multiarch/memmove.c: New file. * sysdeps/sparc/sparc64/multiarch/ifunc-memmove.h: Likewise. * sysdeps/sparc/sparc64/multiarch/memcpy-memmove-niagara7.S: Likewise. * sysdeps/sparc/sparc64/multiarch/memmove-ultra1.S: Likewise. * sysdeps/sparc/sparc64/multiarch/rtld-memmove.c: Likewise.
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