spirv-llvm-translator: -> 18.1.0
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GPG Key ID:
42F8B4E30B673606
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@ -1,6 +1,5 @@
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untrusted comment: verify with /etc/ports/opt.pub
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RWSE3ohX2g5d/cIBtq7YOD8wrj+EmaxUNjhEU/u0g/yhVfqFGrBQClqZ5qEc3ggo+s+9lPAFALWXkRWH0MijgHXRaPLNei6btQM=
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SHA256 (Pkgfile) = 25dd3c2d72fe384c0783af2d32839293277851f68367adf097390e300c0c955f
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RWSE3ohX2g5d/R3Ool/OkyzUiCN2CjKOhHs6uMzdCcdw2LuzLSSSjBZTPsa95SpZ4DtH6Uj98ZhJrmX1VMSwp4n9sWJlGitHzgE=
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SHA256 (Pkgfile) = 31329175348c315f78db6f143d35fb5c694e2994a441d4f37de1ddee991d81a5
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SHA256 (.footprint) = cd463b26973c4d27d3224f5f0cc026b48489191c2610d91098c10c033d914000
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SHA256 (spirv-llvm-translator-18.1.0.tar.gz) = 78a770eff24d5ffe2798479845adec4b909cbf058ddc55830ea00fa7d2c1698a
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SHA256 (2388.patch) = 192694755de32ac95461c8c9bfa486b6625507f91435ff6e72d0226c2488a7a5
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@ -1,391 +0,0 @@
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From 506792b25c2d3ec827d8aa49349f6e7b725c56c4 Mon Sep 17 00:00:00 2001
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From: Viktoria Maximova <viktoria.maksimova@intel.com>
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Date: Mon, 26 Feb 2024 18:37:25 +0100
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Subject: [PATCH] [Backport to 18] Support SPV_INTEL_maximum_registers
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extension (#2344)
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Spec:
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KhronosGroup/SPIRV-Registry#235
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---
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include/LLVMSPIRVExtensions.inc | 1 +
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lib/SPIRV/SPIRVReader.cpp | 42 +++++++++
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lib/SPIRV/SPIRVWriter.cpp | 37 +++++++-
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lib/SPIRV/SPIRVWriter.h | 1 +
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lib/SPIRV/libSPIRV/SPIRVEntry.cpp | 3 +
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lib/SPIRV/libSPIRV/SPIRVEntry.h | 19 ++++-
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lib/SPIRV/libSPIRV/SPIRVEnum.h | 6 ++
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lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h | 3 +
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lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 8 ++
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lib/SPIRV/libSPIRV/SPIRVStream.cpp | 1 +
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lib/SPIRV/libSPIRV/SPIRVStream.h | 1 +
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spirv-headers-tag.conf | 2 +-
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.../registerallocmode_maxreg_extension.ll | 85 +++++++++++++++++++
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13 files changed, 206 insertions(+), 3 deletions(-)
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create mode 100644 test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll
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diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc
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index 780faec576..b884e37230 100644
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--- a/include/LLVMSPIRVExtensions.inc
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+++ b/include/LLVMSPIRVExtensions.inc
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@@ -69,3 +69,4 @@ EXT(SPV_INTEL_fpga_argument_interfaces)
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EXT(SPV_INTEL_fpga_latency_control)
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EXT(SPV_INTEL_fp_max_error)
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EXT(SPV_INTEL_cache_controls)
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+EXT(SPV_INTEL_maximum_registers)
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diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
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index 0502d4e613..daf9fb6a21 100644
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--- a/lib/SPIRV/SPIRVReader.cpp
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+++ b/lib/SPIRV/SPIRVReader.cpp
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@@ -4306,6 +4306,48 @@ bool SPIRVToLLVM::transMetadata() {
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F->setMetadata(kSPIR2MD::IntelFPGAIPInterface,
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MDNode::get(*Context, InterfaceMDVec));
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}
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+ if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersINTEL)) {
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+ NamedMDNode *ExecModeMD =
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+ M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
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+
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+ SmallVector<Metadata *, 4> ValueVec;
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+ ValueVec.push_back(ConstantAsMetadata::get(F));
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+ ValueVec.push_back(
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+ ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
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+ ValueVec.push_back(
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+ ConstantAsMetadata::get(getUInt32(M, EM->getLiterals()[0])));
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+ ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
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+ }
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+ if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersIdINTEL)) {
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+ NamedMDNode *ExecModeMD =
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+ M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
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+
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+ SmallVector<Metadata *, 4> ValueVec;
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+ ValueVec.push_back(ConstantAsMetadata::get(F));
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+ ValueVec.push_back(
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+ ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
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+
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+ auto *ExecOp = BF->getModule()->getValue(EM->getLiterals()[0]);
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+ ValueVec.push_back(
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+ MDNode::get(*Context, ConstantAsMetadata::get(cast<ConstantInt>(
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+ transValue(ExecOp, nullptr, nullptr)))));
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+ ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
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+ }
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+ if (auto *EM =
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+ BF->getExecutionMode(ExecutionModeNamedMaximumRegistersINTEL)) {
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+ NamedMDNode *ExecModeMD =
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+ M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
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+
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+ SmallVector<Metadata *, 4> ValueVec;
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+ ValueVec.push_back(ConstantAsMetadata::get(F));
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+ ValueVec.push_back(
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+ ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
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+
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+ assert(EM->getLiterals()[0] == 0 &&
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+ "Invalid named maximum number of registers");
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+ ValueVec.push_back(MDString::get(*Context, "AutoINTEL"));
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+ ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
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+ }
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}
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NamedMDNode *MemoryModelMD =
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M->getOrInsertNamedMetadata(kSPIRVMD::MemoryModel);
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diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
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index ba25f210f6..55a66c1e64 100644
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--- a/lib/SPIRV/SPIRVWriter.cpp
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+++ b/lib/SPIRV/SPIRVWriter.cpp
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@@ -977,7 +977,10 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) {
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transFPGAFunctionMetadata(BF, F);
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- transFunctionMetadataAsUserSemanticDecoration(BF, F);
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+ if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_maximum_registers))
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+ transFunctionMetadataAsExecutionMode(BF, F);
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+ else
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+ transFunctionMetadataAsUserSemanticDecoration(BF, F);
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transAuxDataInst(BF, F);
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@@ -1118,6 +1121,38 @@ void LLVMToSPIRVBase::transFPGAFunctionMetadata(SPIRVFunction *BF,
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transMetadataDecorations(FDecoMD, BF);
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}
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+void LLVMToSPIRVBase::transFunctionMetadataAsExecutionMode(SPIRVFunction *BF,
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+ Function *F) {
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+ SmallVector<MDNode *, 1> RegisterAllocModeMDs;
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+ F->getMetadata("RegisterAllocMode", RegisterAllocModeMDs);
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+
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+ for (unsigned I = 0; I < RegisterAllocModeMDs.size(); I++) {
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+ auto *RegisterAllocMode = RegisterAllocModeMDs[I]->getOperand(0).get();
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+ if (isa<MDString>(RegisterAllocMode)) {
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+ StringRef Str = getMDOperandAsString(RegisterAllocModeMDs[I], 0);
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+ NamedMaximumNumberOfRegisters NamedValue =
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+ SPIRVNamedMaximumNumberOfRegistersNameMap::rmap(Str.str());
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+ BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
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+ OpExecutionMode, BF, ExecutionModeNamedMaximumRegistersINTEL,
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+ NamedValue)));
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+ } else if (isa<MDNode>(RegisterAllocMode)) {
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+ auto *RegisterAllocNodeMDOp =
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+ getMDOperandAsMDNode(RegisterAllocModeMDs[I], 0);
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+ int Num = getMDOperandAsInt(RegisterAllocNodeMDOp, 0);
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+ auto *Const =
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+ BM->addConstant(transType(Type::getInt32Ty(F->getContext())), Num);
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+ BF->addExecutionMode(BM->add(new SPIRVExecutionModeId(
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+ BF, ExecutionModeMaximumRegistersIdINTEL, Const->getId())));
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+ } else {
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+ int64_t RegisterAllocVal =
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+ mdconst::dyn_extract<ConstantInt>(RegisterAllocMode)->getZExtValue();
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+ BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
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+ OpExecutionMode, BF, ExecutionModeMaximumRegistersINTEL,
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+ RegisterAllocVal)));
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+ }
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+ }
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+}
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+
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void LLVMToSPIRVBase::transFunctionMetadataAsUserSemanticDecoration(
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SPIRVFunction *BF, Function *F) {
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if (auto *RegisterAllocModeMD = F->getMetadata("RegisterAllocMode")) {
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diff --git a/lib/SPIRV/SPIRVWriter.h b/lib/SPIRV/SPIRVWriter.h
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index cafff7f2c8..344a77f8fc 100644
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--- a/lib/SPIRV/SPIRVWriter.h
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+++ b/lib/SPIRV/SPIRVWriter.h
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@@ -131,6 +131,7 @@ class LLVMToSPIRVBase : protected BuiltinCallHelper {
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SPIRVFunction *transFunctionDecl(Function *F);
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void transVectorComputeMetadata(Function *F);
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void transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F);
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+ void transFunctionMetadataAsExecutionMode(SPIRVFunction *BF, Function *F);
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void transFunctionMetadataAsUserSemanticDecoration(SPIRVFunction *BF,
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Function *F);
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void transAuxDataInst(SPIRVFunction *BF, Function *F);
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diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
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index a522d71943..b7ea5ff715 100644
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--- a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
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+++ b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
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@@ -660,6 +660,9 @@ void SPIRVExecutionMode::decode(std::istream &I) {
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case ExecutionModeSchedulerTargetFmaxMhzINTEL:
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case ExecutionModeRegisterMapInterfaceINTEL:
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case ExecutionModeStreamingInterfaceINTEL:
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+ case ExecutionModeMaximumRegistersINTEL:
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+ case ExecutionModeMaximumRegistersIdINTEL:
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+ case ExecutionModeNamedMaximumRegistersINTEL:
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WordLiterals.resize(1);
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break;
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default:
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diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.h b/lib/SPIRV/libSPIRV/SPIRVEntry.h
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index 7218e4ac32..7c0afc903b 100644
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--- a/lib/SPIRV/libSPIRV/SPIRVEntry.h
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+++ b/lib/SPIRV/libSPIRV/SPIRVEntry.h
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@@ -696,6 +696,17 @@ class SPIRVExecutionMode : public SPIRVAnnotation {
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}
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}
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+ std::optional<ExtensionID> getRequiredExtension() const override {
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+ switch (static_cast<unsigned>(ExecMode)) {
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+ case ExecutionModeMaximumRegistersINTEL:
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+ case ExecutionModeMaximumRegistersIdINTEL:
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+ case ExecutionModeNamedMaximumRegistersINTEL:
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+ return ExtensionID::SPV_INTEL_maximum_registers;
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+ default:
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+ return {};
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+ }
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+ }
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+
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protected:
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_SPIRV_DCL_ENCDEC
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SPIRVExecutionModeKind ExecMode;
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@@ -757,6 +768,11 @@ class SPIRVComponentExecutionModes {
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return IsDenorm(EMK) || IsRoundingMode(EMK) || IsFPMode(EMK) ||
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IsOtherFP(EMK);
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};
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+ auto IsMaxRegisters = [&](auto EMK) {
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+ return EMK == ExecutionModeMaximumRegistersINTEL ||
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+ EMK == ExecutionModeMaximumRegistersIdINTEL ||
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+ EMK == ExecutionModeNamedMaximumRegistersINTEL;
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+ };
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auto IsCompatible = [&](SPIRVExecutionMode *EM0, SPIRVExecutionMode *EM1) {
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if (EM0->getTargetId() != EM1->getTargetId())
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return true;
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@@ -770,7 +786,8 @@ class SPIRVComponentExecutionModes {
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return true;
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return !(IsDenorm(EMK0) && IsDenorm(EMK1)) &&
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!(IsRoundingMode(EMK0) && IsRoundingMode(EMK1)) &&
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- !(IsFPMode(EMK0) && IsFPMode(EMK1));
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+ !(IsFPMode(EMK0) && IsFPMode(EMK1)) &&
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+ !(IsMaxRegisters(EMK0) && IsMaxRegisters(EMK1));
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};
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for (auto I = ExecModes.begin(); I != ExecModes.end(); ++I) {
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assert(IsCompatible(ExecMode, (*I).second) &&
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diff --git a/lib/SPIRV/libSPIRV/SPIRVEnum.h b/lib/SPIRV/libSPIRV/SPIRVEnum.h
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index d1bbc83626..ccabddb597 100644
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--- a/lib/SPIRV/libSPIRV/SPIRVEnum.h
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+++ b/lib/SPIRV/libSPIRV/SPIRVEnum.h
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@@ -291,6 +291,12 @@ template <> inline void SPIRVMap<SPIRVExecutionModeKind, SPIRVCapVec>::init() {
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{CapabilityFPGAKernelAttributesINTEL});
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ADD_VEC_INIT(ExecutionModeNamedBarrierCountINTEL,
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{CapabilityVectorComputeINTEL});
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+ ADD_VEC_INIT(ExecutionModeMaximumRegistersINTEL,
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+ {CapabilityRegisterLimitsINTEL});
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+ ADD_VEC_INIT(ExecutionModeMaximumRegistersIdINTEL,
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+ {CapabilityRegisterLimitsINTEL});
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+ ADD_VEC_INIT(ExecutionModeNamedMaximumRegistersINTEL,
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+ {CapabilityRegisterLimitsINTEL});
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}
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template <> inline void SPIRVMap<SPIRVMemoryModelKind, SPIRVCapVec>::init() {
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diff --git a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
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index 080b8bcd86..9930349dbd 100644
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--- a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
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+++ b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
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@@ -73,6 +73,9 @@ inline bool isValid(spv::ExecutionModel V) {
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case ExecutionModelCallableKHR:
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case ExecutionModeRegisterMapInterfaceINTEL:
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case ExecutionModeStreamingInterfaceINTEL:
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+ case ExecutionModeMaximumRegistersINTEL:
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+ case ExecutionModeMaximumRegistersIdINTEL:
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+ case ExecutionModeNamedMaximumRegistersINTEL:
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return true;
|
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default:
|
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return false;
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diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
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index 2635c974be..53fc2e192a 100644
|
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--- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
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+++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
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@@ -637,6 +637,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
|
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add(CapabilityFPGAArgumentInterfacesINTEL, "FPGAArgumentInterfacesINTEL");
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add(CapabilityFPGALatencyControlINTEL, "FPGALatencyControlINTEL");
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add(CapabilityFPMaxErrorINTEL, "FPMaxErrorINTEL");
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+ add(CapabilityRegisterLimitsINTEL, "RegisterLimitsINTEL");
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// From spirv_internal.hpp
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add(internal::CapabilityFastCompositeINTEL, "FastCompositeINTEL");
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add(internal::CapabilityOptNoneINTEL, "OptNoneINTEL");
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@@ -691,6 +692,13 @@ template <> inline void SPIRVMap<HostAccessQualifier, std::string>::init() {
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}
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SPIRV_DEF_NAMEMAP(HostAccessQualifier, SPIRVHostAccessQualifierNameMap)
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|
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+template <>
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+inline void SPIRVMap<NamedMaximumNumberOfRegisters, std::string>::init() {
|
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+ add(NamedMaximumNumberOfRegistersAutoINTEL, "AutoINTEL");
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+}
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+SPIRV_DEF_NAMEMAP(NamedMaximumNumberOfRegisters,
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+ SPIRVNamedMaximumNumberOfRegistersNameMap);
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+
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} /* namespace SPIRV */
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#endif // SPIRV_LIBSPIRV_SPIRVNAMEMAPENUM_H
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diff --git a/lib/SPIRV/libSPIRV/SPIRVStream.cpp b/lib/SPIRV/libSPIRV/SPIRVStream.cpp
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index 7b785b5b55..7dfbdddbfa 100644
|
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--- a/lib/SPIRV/libSPIRV/SPIRVStream.cpp
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+++ b/lib/SPIRV/libSPIRV/SPIRVStream.cpp
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@@ -147,6 +147,7 @@ SPIRV_DEF_ENCDEC(SPIRVDebugExtOpKind)
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SPIRV_DEF_ENCDEC(NonSemanticAuxDataOpKind)
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SPIRV_DEF_ENCDEC(InitializationModeQualifier)
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SPIRV_DEF_ENCDEC(HostAccessQualifier)
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+SPIRV_DEF_ENCDEC(NamedMaximumNumberOfRegisters)
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SPIRV_DEF_ENCDEC(LinkageType)
|
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|
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// Read a string with padded 0's at the end so that they form a stream of
|
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diff --git a/lib/SPIRV/libSPIRV/SPIRVStream.h b/lib/SPIRV/libSPIRV/SPIRVStream.h
|
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index 0a788044a6..21cb51a3a0 100644
|
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--- a/lib/SPIRV/libSPIRV/SPIRVStream.h
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+++ b/lib/SPIRV/libSPIRV/SPIRVStream.h
|
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@@ -231,6 +231,7 @@ SPIRV_DEC_ENCDEC(SPIRVDebugExtOpKind)
|
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SPIRV_DEC_ENCDEC(NonSemanticAuxDataOpKind)
|
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SPIRV_DEC_ENCDEC(InitializationModeQualifier)
|
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SPIRV_DEC_ENCDEC(HostAccessQualifier)
|
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+SPIRV_DEC_ENCDEC(NamedMaximumNumberOfRegisters)
|
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SPIRV_DEC_ENCDEC(LinkageType)
|
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|
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const SPIRVEncoder &operator<<(const SPIRVEncoder &O, const std::string &Str);
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diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf
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index 7fae55f32b..3c34bf8933 100644
|
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--- a/spirv-headers-tag.conf
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+++ b/spirv-headers-tag.conf
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@@ -1 +1 @@
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-1c6bb2743599e6eb6f37b2969acc0aef812e32e3
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+b73e168ca5e123dcf3dea8a34b19a5130f421ae1
|
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diff --git a/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll b/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll
|
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new file mode 100644
|
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index 0000000000..1dfc768ffe
|
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--- /dev/null
|
||||
+++ b/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll
|
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@@ -0,0 +1,85 @@
|
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+; RUN: llvm-as %s -o %t.bc
|
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+; RUN: llvm-spirv -spirv-text --spirv-ext=+SPV_INTEL_maximum_registers %t.bc
|
||||
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
|
||||
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_maximum_registers -o %t.spv
|
||||
+; RUN: llvm-spirv -r %t.spv -spirv-target-env=SPV-IR -o - | llvm-dis -o %t.rev.ll
|
||||
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
|
||||
+
|
||||
+; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC0:]] "main_l3"
|
||||
+; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC1:]] "main_l6"
|
||||
+; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC2:]] "main_l9"
|
||||
+; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC3:]] "main_l13"
|
||||
+; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC4:]] "main_l19"
|
||||
+
|
||||
+; CHECK-SPIRV: ExecutionMode [[#FUNC0]] 6461 2
|
||||
+; CHECK-SPIRV: ExecutionMode [[#FUNC1]] 6461 1
|
||||
+; CHECK-SPIRV: ExecutionMode [[#FUNC2]] 6463 0
|
||||
+; CHECK-SPIRV: ExecutionModeId [[#FUNC3]] 6462 [[#Const3:]]
|
||||
+; CHECK-SPIRV: TypeInt [[#TypeInt:]] 32 0
|
||||
+; CHECK-SPIRV: Constant [[#TypeInt]] [[#Const3]] 3
|
||||
+
|
||||
+; CHECK-SPIRV-NOT: ExecutionMode [[#FUNC4]]
|
||||
+
|
||||
+; CHECK-LLVM: !spirv.ExecutionMode = !{![[#FLAG0:]], ![[#FLAG1:]], ![[#FLAG2:]], ![[#FLAG3:]]}
|
||||
+; CHECK-LLVM: ![[#FLAG0]] = !{ptr @main_l3, i32 6461, i32 2}
|
||||
+; CHECK-LLVM: ![[#FLAG1]] = !{ptr @main_l6, i32 6461, i32 1}
|
||||
+; CHECK-LLVM: ![[#FLAG2]] = !{ptr @main_l9, i32 6463, !"AutoINTEL"}
|
||||
+; CHECK-LLVM: ![[#FLAG3]] = !{ptr @main_l13, i32 6462, ![[#VAL:]]}
|
||||
+; CHECK-LLVM: ![[#VAL]] = !{i32 3}
|
||||
+
|
||||
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
|
||||
+target triple = "spir64"
|
||||
+
|
||||
+; Function Attrs: noinline nounwind optnone
|
||||
+define weak dso_local spir_kernel void @main_l3() #0 !RegisterAllocMode !10 {
|
||||
+newFuncRoot:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+; Function Attrs: noinline nounwind optnone
|
||||
+define weak dso_local spir_kernel void @main_l6() #0 !RegisterAllocMode !11 {
|
||||
+newFuncRoot:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+; Function Attrs: noinline nounwind optnone
|
||||
+define weak dso_local spir_kernel void @main_l9() #0 !RegisterAllocMode !12 {
|
||||
+newFuncRoot:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+; Function Attrs: noinline nounwind optnone
|
||||
+define weak dso_local spir_kernel void @main_l13() #0 !RegisterAllocMode !13 {
|
||||
+newFuncRoot:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+; Function Attrs: noinline nounwind optnone
|
||||
+define weak dso_local spir_kernel void @main_l19() #0 {
|
||||
+newFuncRoot:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+attributes #0 = { noinline nounwind optnone }
|
||||
+
|
||||
+
|
||||
+!opencl.compiler.options = !{!0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0}
|
||||
+!spirv.Source = !{!2, !3, !3, !3, !3, !3, !2, !3, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2}
|
||||
+!llvm.module.flags = !{!4, !5, !6, !7, !8}
|
||||
+!spirv.MemoryModel = !{!9, !9, !9, !9, !9, !9}
|
||||
+!spirv.ExecutionMode = !{}
|
||||
+
|
||||
+!0 = !{}
|
||||
+!2 = !{i32 4, i32 200000}
|
||||
+!3 = !{i32 3, i32 200000}
|
||||
+!4 = !{i32 1, !"wchar_size", i32 4}
|
||||
+!5 = !{i32 7, !"openmp", i32 50}
|
||||
+!6 = !{i32 7, !"openmp-device", i32 50}
|
||||
+!7 = !{i32 8, !"PIC Level", i32 2}
|
||||
+!8 = !{i32 7, !"frame-pointer", i32 2}
|
||||
+!9 = !{i32 2, i32 2}
|
||||
+!10 = !{i32 2}
|
||||
+!11 = !{i32 1}
|
||||
+!12 = !{!"AutoINTEL"}
|
||||
+!13 = !{!14}
|
||||
+!14 = !{i32 3}
|
||||
|
|
@ -5,15 +5,12 @@
|
|||
|
||||
name=spirv-llvm-translator
|
||||
version=18.1.0
|
||||
release=1
|
||||
source=(https://github.com/KhronosGroup/SPIRV-LLVM-Translator/archive/v$version/$name-$version.tar.gz
|
||||
2388.patch)
|
||||
release=2
|
||||
source=(https://github.com/KhronosGroup/SPIRV-LLVM-Translator/archive/v$version/$name-$version.tar.gz)
|
||||
|
||||
build() {
|
||||
prt-get isinst ccache && PATH="$(echo ${PATH} | awk -v RS=: -v ORS=: '/ccache/ {next} {print}' | sed 's/:*$//')"
|
||||
|
||||
patch -Rp1 -d SPIRV-LLVM-Translator-$version -i $SRC/2388.patch
|
||||
|
||||
cmake -S SPIRV-LLVM-Translator-$version -B build -G Ninja $PKGMK_SLT \
|
||||
-D CMAKE_INSTALL_PREFIX=/usr \
|
||||
-D CMAKE_INSTALL_LIBDIR=lib \
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user